This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-018013, filed Jan. 26, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device having an insulated gate structure, such as an IGBT (Insulated Gate Bipolar Transistor), or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
2. Description of the Related Art
An IGBT is a voltage-controlled device having both a high-speed switching characteristic like a MOSFET and a high power handling capability like a bipolar transistor. In recent years, IGBTs are widely used in power converters and switched mode power supplies in the power electronics field.
An explanation will be given of the structure of a conventional IGBT, taking a vertical type n-channel IGBT as an example, with reference to FIGS. 23 and 24. In general, arrays of IGBT unit cells are disposed in stripes in the central area (corresponding to an active area) other than the peripheral region (corresponding to a junction-termination region) on a semiconductor substrate. For the sake of simplicity, the IGBT will be partly explained, focusing on necessary portions.
FIG. 23 is a sectional view schematically showing the junction-termination region and a portion of the active area near there, of a conventional IGBT. FIG. 24 is a plan view taken along line XXIVxe2x80x94XXIV in FIG. 23.
As shown in FIG. 23, p-base layers 102 are formed by diffusion in the surface of an nxe2x88x92-base layer 101. N+-emitter layers 103 are formed by diffusion in the surfaces of the p-base layers 102. A gate electrode 106 is formed through a gate insulating film 107 on each of the portions of the p-base layers 102 between the nxe2x88x92-base layer 101 and the n+-emitter layers 103. An emitter electrode 109 is disposed in ohmic-contact with the n+-emitter layers 103 and the p-base layers 102. A p+-emitter layer 105 is formed through an n-buffer layer 104 on the bottom side of the nxe2x88x92-base layer 101. A collector electrode 110 is disposed in ohmic-contact with the p+-emitter layer 105.
As shown in FIG. 24, a p+-ring layer 111 is formed in the junction-termination region and surrounds the central area (the active area) in which the arrays of IGBT unit cells are formed. The p+-ring layer 111 is electrically connected to the emitter electrode 109 through a connection electrode 109b, which is integral with the emitter electrode 109. A ring-like n+-diffusion layer 114 is formed in the junction-termination region, along the peripheral edge thereof. A ring-like stopper electrode 115 in an electrically floating state is disposed on the n+-diffusion layer 114. The n+-diffusion layer 114 and the stopper electrode 115 constitute an equi-potential ring 116. A pxe2x88x92-RESURF (Reduced Surface Field) layer 112 is formed between the p+-ring layer 111 and the n+-diffusion layer 114 and in contact with the p+-ring layer 111. The surface of the nxe2x88x92-base layer 101 from the p+-ring layer 111 to the n+-diffusion layer 114 is covered with an insulating protection film 108.
When the IGBT is turned on, the following operation is performed. Specifically, while a positive bias is applied between the collector electrode 110 and the emitter electrode 109 (the plus is on the collector electrode 110 side), a positive voltage (a positive bias) relative to the emitter electrode 109 is applied to the gate electrodes 106. By doing so, n-inversion layers (not shown) are formed near the interfaces between the p-base layers 102 and the gate insulating films 107, and thus electrons are injected from the n+-emitter layers 103 into the nxe2x88x92-base layer 101. In accordance with the injection amount of the electrons, holes are injected from the p+-emitter layer 105 into the nxe2x88x92-base layer 101. As a result, the nxe2x88x92-base layer 101 is filled with carriers and causes a conductivity modulation, and thus the resistance of the nxe2x88x92-base layer 101 decreases to bring the IGBT into an ON-state.
On the other hand, when the IGBT is turned off, the following operation is performed. Specifically, in the ON-state described above, a negative bias is applied to the gate electrodes 106. By doing so, the n-inversion layers near the interfaces between the p-base layers 102 and the gate insulating films 107 disappear, and thus electrons stop being injected from the n+-emitter layers 103 into the nxe2x88x92-base layer 101. As a result, holes also stop being injected from the p+-emitter layer 105 into the nxe2x88x92-base layer 101. Then, carriers filling the nxe2x88x92-base layer 101 are exhausted, and depletion layers expand from the junctions between the p-base layers 102 and the nxe2x88x92-base layer 101 to bring the IGBT into an OFF-state.
During the turn-off operation, holes accumulated in the nxe2x88x92-base layer 101 are exhausted through the p-base layers 102 into the emitter electrode 109, and through the p+-ring layer 111 and the connection electrode 109b into the emitter electrode 109. In general, the p+-ring layer 111 has a considerably large surface area, and a hole current concentrates at the contacting portion of the p+-ring layer 111 with the connection electrode 109b. An excessive part of the hole current, which has not been allowed to flow through the contacting portion, mainly flows through the adjacent p-base layers 102. This current concentration gives rise to an increase in the potential of the p-base layers 102, and occasionally cause it to go beyond the junction potential (which is generally about 0.7V) between the p-base layers 102 and the n+-emitter layers 103. In this case, the device falls in a latched-up state where electrons are directly injected from the n+-emitter layers 103 into the nxe2x88x92-base layer 101. As a result, electric current concentrates at the latched-up portion, thereby bringing about a thermal breakdown of the IGBT.
According to a first aspect of the present invention, there is provided a high breakdown voltage semiconductor device including an active area, and a surrounding region surrounding the active area, comprising:
a first semiconductor layer of a first conductivity type disposed as a semiconductor active layer common to the active area and the surrounding region, the first semiconductor layer having first and second main surfaces opposite to each other;
a second semiconductor layer of a second conductivity type formed in the first main surface of the first semiconductor layer in the active area;
a third semiconductor layer of the first conductivity type formed in a surface of the second semiconductor layer;
a fourth semiconductor layer disposed on or in the second main surface of the first semiconductor layer in the active area;
a gate electrode facing, through a gate insulating film, a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer;
a first main electrode electrically connected to the second semiconductor layer and the third semiconductor layer;
a second main electrode electrically connected to the fourth semiconductor layer;
a ring layer of the second conductivity type formed in the first main surface of the first semiconductor layer and surrounding the active area at a position in the surrounding region adjacent to the active area;
a first low-resistivity layer formed in a surface of the ring layer and having a resistivity lower than that of the ring layer; and
a connection electrode electrically connecting the first low-resistivity layer to the first main electrode.
According to a second aspect of the present invention, there is provided a high breakdown voltage semiconductor device including an active area, and a junction-termination region surrounding the active area, comprising:
a first semiconductor layer of a first conductivity type disposed as a semiconductor active layer common to the active area and the junction-termination region, the first semiconductor layer having first and second main surfaces opposite to each other;
a second semiconductor layer of a second conductivity type formed in the first main surface of the first semiconductor layer in the active area;
a third semiconductor layer of the first conductivity type formed in a surface of the second semiconductor layer;
a fourth semiconductor layer disposed on or in the second main surface of the first semiconductor layer in the active area;
a gate electrode facing, through a gate insulating film, a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer;
a first main electrode electrically connected to the second semiconductor layer and the third semiconductor layer;
a second main electrode electrically connected to the fourth semiconductor layer;
a ring layer of the second conductivity type formed in the first main surface of the first semiconductor layer and surrounding the active area at a position in the junction-termination region adjacent to the active area;
a first low-resistivity layer formed in a surface of the ring layer and having a resistivity lower than that of the ring layer;
a connection electrode electrically connecting the first low-resistivity layer to the first main electrode
a second low-resistivity layer formed in a surface of the second semiconductor layer and having a resistivity lower than that of the second semiconductor layer, the second low-resistivity layer being disposed in contact with the first main electrode and the second and third semiconductor layers, the second low-resistivity layer consisting essentially of a material the same as that of the first low-resistivity layer;
an end layer of the first conductivity type formed in the first main surface of the first semiconductor layer along a peripheral edge of the first semiconductor layer in the junction-termination region, the end layer having a carrier impurity concentration higher than that of the first semiconductor layer; and
a third low-resistivity layer formed in a surface of the end layer and having a resistivity lower than that of the end layer, the third low-resistivity layer consisting essentially of a material the same as that of the first low-resistivity layer.